C8051F960-B-GM Datasheet, PDF (285/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 22.2. RSTSRC: Reset Source
Bit
7
6
5
4
3
2
1
0
Name RTC0RE FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF
Type R/W
R
R/W
R/W
R
R/W
R/W
R
Reset Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Page = 0x0; SFR Address = 0xEF.
Bit Name
Description
Write
Read
7 RTC0RE SmaRTClock Reset Enable 0: Disable SmaRTClock Set to 1 if SmaRTClock
and Flag
as a reset source.
alarm or oscillator fail
1: Enable SmaRTClock as ^{caused the last reset.}
a reset source.
6 FERROR Flash Error Reset Flag.
N/A
Set to 1 if Flash
read/write/erase error
caused the last reset.
5 C0RSEF Comparator0 Reset Enable 0: Disable Comparator0 as Set to 1 if Comparator0
and Flag.
a reset source.
caused the last reset.
1: Enable Comparator0 as
a reset source.
4 SWRSF Software Reset Force and Writing a 1 forces a sys- Set to 1 if last reset was
Flag.
tem reset.
caused by a write to
SWRSF.
3 WDTRSF Watchdog Timer Reset Flag. N/A
Set to 1 if Watchdog Timer
overflow caused the last
reset.
2 MCDRSF Missing Clock Detector
(MCD) Enable and Flag.
0: Disable the MCD.
Set to 1 if Missing Clock
1: Enable the MCD.
Detector timeout caused
The MCD triggers a reset ^{the last reset.}
if a missing clock condition
is detected.
1 PORSF Power-On / Power-Fail
0: Disable the VDD Supply Set to 1 anytime a power-
Reset Flag, and Power-Fail Monitor as a reset source. on or V_DD monitor reset
Reset Enable.
1: Enable the VDD Supply ^occurs.2
Monitor as a reset
source.³
0 PINRSF HW Pin Reset Flag.
N/A
Set to 1 if RST pin caused
the last reset.
Notes:
1. It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2. If PORSF read back 1, the value read from all other bits in this register are indeterminate.
3. Writing a 1 to PORSF before the VDD Supply Monitor is stabilized may generate a system reset.
Rev. 1.0
285