C8051F960-B-GM Datasheet, PDF (345/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
26.5. Setting the LCD Refresh Rate
The clock to the LCD0 module is derived from the SmaRTClock and may be divided down according to the
settings in the LCD0CN register. The LCD refresh rate is derived from the LCD0 clock and can be pro-
grammed using the LCD0DIVH:LCD0DIVL registers. The LCD mux mode must be taken into account
when determining the prescaler value. See the LCD0DIVH/LCD0DIVL register descriptions for more
details. For maximum power savings, choose a slow LCD refresh rate and the minimum LCD0 clock fre-
quency. For the least flicker, choose a fast LCD refresh rate.
SFR Definition 26.8. LCD0CLKDIVH: LCD0 Refresh Rate Prescaler High Byte
Bit
7
6
5
4
3
2
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
1
0
LCD0DIV[9:8]
R/W
0
0
SFR Page = 0x2; SFR Address = 0xAA
Bit
Name
Function
7:2
Unused Read = 000000. Write = Don’t Care.
1:0 LCD0DIV[9:8] LCD Refresh Rate Prescaler.
Sets the LCD refresh rate according to the following equation:
LCD Refresh Rate
=
-------------L----C----D-----0----C----l--o---c--k-----F---r--e---q---u---e---n---c--y---------------
4  mux_mode  LCD0DIV + 1
SFR Definition 26.9. LCD0CLKDIVL: LCD Refresh Rate Prescaler Low Byte
Bit
7
6
5
4
3
2
1
0
Name
LCD0DIV[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xA9
Bit
Name
Function
7:0 LCD0DIV[7:0] LCD Refresh Rate Prescaler.
Sets the LCD refresh rate according to the following equation:
LCD Refresh Rate = _4----------m---L-u---Cx---_-D---m--0--o--C-d---le--o--_-c--k--_---_L^F---r_C--e---_D^q---u-0--e--_D-n---c_I--y-_V-----+-----1---_-
Rev. 1.0
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