C8051F960-B-GM Datasheet, PDF (292/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 23.2. OSCICN: Internal Oscillator Control
Bit
7
6
5
Name
Type
Reset
IOSCEN
R/W
0
IFRDY
R
0
R/W
Varies
SFR Page = 0x0; SFR Address = 0xB2
4
R/W
Varies
3
R/W
Varies
2
R/W
Varies
1
R/W
Varies
0
R/W
Varies
Bit Name
Function
7 IOSCEN Internal Oscillator Enable.
0: Internal oscillator disabled.
1: Internal oscillator enabled.
6
IFRDY Internal Oscillator Frequency Ready Flag.
0: Internal oscillator is not running at its programmed frequency.
1: Internal oscillator is running at its programmed frequency.
5:0 Reserved Must perform read-modify-write.
Notes:
1. Read-modify-write operations such as ORL and ANL must be used to set or clear the enable bit of this
register.
2. OSCBIAS (REG0CN.4) must be set to 1 before enabling the precision internal oscillator.
292
Rev. 1.0