C8051F960-B-GM Datasheet, PDF (203/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 14.2. AES0DCFG: AES Data Configuration
Bit
7
6
5
4
3
2
1
0
Name
OUTSEL[1:0]
XORIN
Type
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xEA; SFR page = 0x2; Not bit-Addressable
Bit
Name
Function
2:1 OUTSEL[1:0] DATA Select.
These bits select the output data source for the AES0YOUT sfr.
00: Direct AES Data
01: AES Data XOR with AES0XIN
10: Inverse Key
11: reserved
0
XORIN
XOR Input Enable.
Setting this bit with enable the XOR data path on the AES input. If enabled,
AES0BIN will be XORed with the AES0XIN and the results will feed into the AES
data input. Clearing this bit to 0 will disable the XOR gate on the input. The con-
tents of AES0BIN will go directly into the AES data input.
Rev. 1.0
203