C8051F960-B-GM Datasheet, PDF (352/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
27.1. Port I/O Modes of Operation
Port pins P0.0–P6.7 use the Port I/O cell shown in Figure 27.2. The supply pin for P1.5–P2.3 is VIORF and
the supply for all other GPIOs is VIO. Each Port I/O cell can be configured by software for analog I/O or
digital I/O using the PnMDIN registers. P7.0 can only be used for digital functtons and is shared with the
C2D signal. On reset, all Port I/O cells default to a digital high impedance state with weak pull-ups enabled.
27.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, external oscillator input/output, or AGND, VREF, or Cur-
rent Reference output should be configured for analog I/O (PnMDIN.n = 0). When a pin is configured for
analog I/O, its weak pullup and digital receiver are disabled. In most cases, software should also disable
the digital output drivers. Port pins configured for analog I/O will always read back a value of 0 regardless
of the actual voltage on the pin.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
27.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the supply or GND rails based on the output
logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only drive
the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high and
low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled when
the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting
WEAKPUD to 1. The user must ensure that digital I/O are always internally or externally pulled or driven to
a valid logic state. Port pins configured for digital I/O always read back the logic state of the Port pad,
regardless of the output logic value of the Port pin.
WEAKPUD
(Weak Pull-Up Disable)
PnMDOUT.x
(1 for push-pull)
(0 for open-drain)
XBARE
(Crossbar
Enable)
Pn.x – Output
Logic Value
(Port Latch or
Crossbar)
Supply
Supply
(WEAK)
PnMDIN.x
(1 for digital)
(0 for analog)
To/From Analog
Peripheral
Pn.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
GND
Figure 27.2. Port I/O Cell Block Diagram
PORT
PAD
352
Rev. 1.0