C8051F960-B-GM Datasheet, PDF (277/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
21. Voltage Regulator (VREG0)
C8051F96x devices include an internal voltage regulator (VREG0) to regulate the internal core supply to
1.8 V from a VDD/DC+ supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are speci-
fied in the Electrical Specifications chapter.
The REG0CN register allows the Precision Oscillator Bias to be disabled, reducing supply current in all
non-sleep power modes. This bias should only be disabled when the precision oscillator is not being used.
The internal regulator (VREG0) is disabled when the device enters sleep mode and remains enabled when
the device enters suspend mode. See Section “19. Power Management” on page 257 for complete details
about low power modes.
SFR Definition 21.1. REG0CN: Voltage Regulator Control
Bit
7
6
5
4
3
2
1
0
Name
OSCBIAS
Type ^R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
1
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC9
Bit Name
Function
7:5 Reserved Read = 000b. Must Write 000b.
4 OSCBIAS _{Precision Oscillator Bias.}
When set to 1, the bias used by the precision oscillator is forced on. If the precision
oscillator is not being used, this bit may be cleared to 0 to to save supply current in
all non-Sleep power modes.
3:0 Reserved Read = 0000b. Must Write 0000b.
21.1. Voltage Regulator Electrical Specifications
See Table 4.17 on page 75 for detailed Voltage Regulator Electrical Specifications.
Rev. 1.0
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