C8051F960-B-GM Datasheet, PDF (146/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
11. Direct Memory Access (DMA0)
An on-chip direct memory access (DMA0) is included on the C8051F96x devices. The DMA0 subsystem
allows autonomous variable-length data transfers between XRAM and peripheral SFR registers without
CPU intervention. During DMA0 operation, the CPU is free to perform some other tasks. In order to save
total system power consumption, the CPU and flash can be powered down. DMA0 improves the system
performance and efficiency with high data throughput peripherals.
DMA0 contains seven independent channels, common control registers, and a DMA0 Engine (see
Figure 11.1). Each channel includes a register that assigns a peripheral to the channel, a channel control
register, and a set of SFRs that include XRAM address information and SFR address information used by
the channel during a data transfer. The DMA0 architecture is described in detail in Section 11.1.
The DMA0 in C8051F96x devices supports four peripherals: AES0, ENC0, CRC1, and SPI1. Peripherals
with DMA0 capability should be configured to work with the DMA0 through their own registers. The DMA0
provides up to seven channels, and each channel can be configured for one of nine possible data transfer
functions:
 XRAM to ENC0L/M/H
 ENC0L/M/H sfrs to XRAM
 XRAM to CRC1IN sfr
 XRAM to SPI1DAT sfr
 SPI1DAT sfr to XRAM
 XRAM to AES0KIN sfr
 XRAM to AES0BIN sfr
 XRAM to AES0XIN sfr
 AES0YOUT sfr to XRAM
The DMA0 subsystem signals the MCU through a set of interrupt service routine flags. Interrupts can be
generated when the DMA0 transfers half of the data length or full data length on any channel.
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