C8051F960-B-GM Datasheet, PDF (78/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
5. SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode
The ADC0 on C8051F96x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive-approximation-regis-
ter (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an
autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate sam-
ples, then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accu-
mulator that can automatically oversample and average the ADC results. See Section 5.4 for more details
on using the ADC in 12-bit mode.
The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in
Single-ended mode and may be configured to measure various different signals using the analog multi-
plexer described in “5.7. ADC0 Analog Multiplexer” on page 95. The voltage reference for the ADC is
selected as described in “5.9. Voltage and Ground Reference Options” on page 100.
ADC0CN
ADC0TK
ADC0PWR
Burst Mode Logic
VDD
From
AMUX0
AIN+
10/12-Bit
SAR
ADC
000
Start
Conversion ⁰⁰¹
010
011
100
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
16-Bit Accumulator
ADC0LTH ADC0LTL
AD0WINT
Window
Compare
32 _Logic
ADC0CF
ADC0GTH ADC0GTL
Figure 5.1. ADC0 Functional Block Diagram
5.1. Output Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the
ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the
setting of the AD0SJST[2:0]. When the repeat count is set to 1, conversion codes are represented as 10-
bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example codes are shown below
for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to 0.
78
Rev. 1.0