C8051F960-B-GM Datasheet, PDF (91/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte
Bit
7
6
5
4
3
2
1
0
Name
ADC0[15:8]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBE
Bit Name
Description
Read
Write
7:0 ADC0[15:8] ADC0 Data Word High
Byte.
Most Significant Byte of the Set the most significant
16-bit ADC0 Accumulator byte of the 16-bit ADC0
formatted according to the Accumulator to the value
settings in AD0SJST[2:0]. written.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be zeros. This register
should not be written when the SYNC bit is set to 1.
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte
Bit
7
6
5
4
3
2
1
0
Name
ADC0[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBD;
Bit Name
Description
Read
Write
7:0 ADC0[7:0] ADC0 Data Word Low
Byte.
Least Significant Byte of the
16-bit ADC0 Accumulator
formatted according to the
settings in AD0SJST[2:0].
Set the least significant
byte of the 16-bit ADC0
Accumulator to the value
written.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be the least significant bits of
the accumulator high byte. This register should not be written when the SYNC bit is set to 1.
5.6. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
Rev. 1.0
91