C8051F960-B-GM Datasheet, PDF (348/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
26.7. Advanced LCD Optimizations
The special function registers described in this section should be left at their reset value for most systems.
Some systems with specific low power or large load requirments will benefit from tweaking the values in
these registers to achieve minimum power consumption or maximum drive level.
SFR Definition 26.12. LCD0CF: LCD0 Configuration
Bit
7
6
5
4
3
2
1
0
Name
CMPBYP
Type ^R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xA5
Bit
Name
Function
7:6 Reserved Read = 00b. Must write 00b.
5
CMPBYP _{VLCD/VIO Supply Comparator Disable.}
Setting this bit to ‘1’ disables the supply voltage comparator which determines if the
VIO supply is lower than VLCD. This comparator should only be disabled, as a
power saving measure, if VIO is internally or externally shorted to VBAT.
4:0 Reserved Read = 00b. Must write 00000b.
SFR Definition 26.13. LCD0CHPCN: LCD0 Charge Pump Control
Bit
7
6
5
4
3
2
1
0
Name
Type ^R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
1
0
0
1
0
1
1
SFR Page = 0x2; SFR Address = 0xB5
Bit
Name
7:0 Reserved Must write 0x4B.
Function
348
Rev. 1.0