C8051F960-B-GM Datasheet, PDF (325/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 25.5. PC0DCH: PC0 Debounce Configuration High
Bit
7
6
5
4
3
2
1
0
Name
PC0DCH[7:0]
Type
R/W
Reset
0
0
0
0
0
1
0
0
SFR Address = 0xFA; SFR Page = 0x2
Bit
Name
Function
7:0
PC0DCH[7:0] Pulse Counter Debounce High
Number of cumulative good samples seen by the integrator before recogniz-
ing the input as high. Sampling a low will decrement the count while sam-
pling a high will increment the count. The actual value used is PC0DCH plus
one. Switch bounce produces a random looking signal. The worst case
would be to bounce low at each sample point and not start incrementing the
integrator until the switch bounce settled. Therefore, minimum pulse width
should account for twice the debounce time. For example, using a sample
rate of 250 µs and a PC0DCH value of 0x13 will look for 20 cumulative
highs before recognizing the input as high (250 µs x (16+3+1) = 5 ms).
Rev. 1.0
325