C8051F960-B-GM Datasheet, PDF (423/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 30.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing (See Figure 30.8 and Figure 30.9)
T_MCKH
SCK High Time
1 x T_SYSCLK
—
ns
T_MCKL
SCK Low Time
1 x T_SYSCLK
—
ns
T_MIS
MISO Valid to SCK Shift Edge
1 x T_SYSCLK + 20
—
ns
T_MIH
SCK Shift Edge to MISO Change
0
—
ns
Slave Mode Timing (See Figure 30.10 and Figure 30.11)
T_SE
T_SD
T_SEZ
T_SDZ
T_CKH
T_CKL
T_SIS
T_SIH
T_SOH
T_SLH
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change 
(CKPHA = 1 ONLY)
2 x T_SYSCLK
2 x T_SYSCLK
—
—
5 x T_SYSCLK
5 x T_SYSCLK
2 x T_SYSCLK
2 x T_SYSCLK
—
6 x T_SYSCLK
—
ns
—
ns
4 x T_SYSCLK ns
4 x T_SYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x T_SYSCLK ns
8 x T_SYSCLK ns
Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
Rev. 1.0
423