C8051F960-B-GM Datasheet, PDF (244/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
18. Flash Memory
On-chip, re-programmable flash memory is included for program code and non-volatile data storage. The
flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft-
ware using the MOVX write instruction. Once cleared to logic 0, a flash bit must be erased to set it back to
logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and
erase operations are automatically timed by hardware for proper execution; data polling to determine the
end of the write/erase operations is not required. Code execution is stalled during flash write/erase opera-
tions. Refer to Table 4.8 for complete flash memory electrical characteristics.
18.1. Programming the Flash Memory
The simplest means of programming the flash memory is through the C2 interface using programming
tools provided by Silicon Laboratories or a third party vendor. This is the only means for programming a
non-initialized device. For details on the C2 commands to program flash memory, see Section “34. C2
Interface” on page 486.
The flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before programming flash memory using
MOVX, flash programming operations must be enabled by: (1) setting the PSWE Program Store Write
Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target flash memory); and (2) Writing the
flash key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared by
software. For detailed guidelines on programming flash from firmware, please see Section “18.5. Flash
Write and Erase Guidelines” on page 250.
To ensure the integrity of the flash contents, the on-chip VDD Monitor must be enabled and enabled as a
reset source in any system that includes code that writes and/or erases flash memory from software. Fur-
thermore, there should be no delay between enabling the V_DD Monitor and enabling the V_DD Monitor as a
reset source. Any attempt to write or erase flash memory while the V_DD Monitor is disabled, or not enabled
as a reset source, will cause a Flash Error device reset.
18.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a flash
write or erase is attempted before the key codes have been written properly. The flash lock resets after
each write or erase; the key codes must be written again before a following flash operation can be per-
formed. The FLKEY register is detailed in SFR Definition 18.4.
18.1.2. Flash Erase Procedure
The flash memory is organized in 1024-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 1024-byte page, perform the following steps:
1. Save current interrupt state and disable interrupts.
2. Set the PSEE bit (register PSCTL).
3. Set the PSWE bit (register PSCTL).
4. If writing to an address in Banks 1, 2, or 3, set the COBANK[1:0] bits (register PSBANK) for the
appropriate bank.
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a data byte to any location within the 1024-byte page to be erased.
8. Clear the PSWE and PSEE bits.
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