C8051F960-B-GM Datasheet, PDF (255/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 18.5. FLSCL: Flash Scale
Bit
7
6
5
4
3
2
1
0
Name
BYPASS
Type
R
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB6
Bit Name
7 Reserved Always Write to 0.
Function
6 BYPASS Flash Read Timing One-Shot Bypass.
0: The one-shot determines the flash read time.
1: The system clock determines the flash read time.
Leaving the one-shot enabled will provide the lowest power consumption up to
25 MHz.
5:0 Reserved Always Write to 000000.
Note: Operations which clear the BYPASS bit do not need to be immediately followed by a benign 3-byte instruction.
For code compatibility with C8051F930/31/20/21 devices, a benign 3-byte instruction whose third byte is a
don't care should follow the clear operation. See the C8051F93x-C8051F92x data sheet for more details.
SFR Definition 18.6. FLWR: Flash Write Only
Bit
7
6
5
4
3
2
1
0
Name
FLWR[7:0]
Type
W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xE5
Bit Name
Function
7:0 FLWR[7:0] Flash Write Only.
All writes to this register have no effect on system operation.
Rev. 1.0
255