C8051F960-B-GM Datasheet, PDF (258/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
19.1. Normal Mode
The MCU is fully functional in Normal Mode. Figure 19.1 shows the on-chip power distribution to various
peripherals. There are three supply voltages powering various sections of the chip: VBAT, DCOUT, and the
1.8 V internal core supply (output of VREG0). All analog peripherals are directly powered from the VBAT
pin. All digital peripherals and the CIP-51 core are powered from the 1.8 V internal core supply (output of
VREG0). The Pulse counter, RAM, PMU0, and the SmaRTClock are powered from the internal core supply
when the device is in normal mode. The input to VREG0 is controlled by software and depends on the set-
tings of the power select switch. The power select switch may be configured to power VREG0 from VBAT
or from the output of the DC0.
VBATDC
GNDDC
IND
DC0
Buck
Converter
Pulse
Counter
RAM
PMU0
SmaRTClock
VDC
VBAT
1.8 to 3.6 V
1.9 V
VIO/VIORF must be <= VBAT
Power
Select
Sleep
VREG0
Analog Peripherals
VREF
LCD
A
M
U
ADC
+
+
X
-
-
TEMP
SENSOR
VOLTAGE
COMPARATORS
Digital Peripherals
Flash
Active/Idle/ ^{1.8 V}
Stop/Suspend
CIP-51
Core
AES
UART
SPI
Timers
SMBus
VIO
VIORF
Figure 19.1. C8051F96x Power Distribution
19.2. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
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Rev. 1.0