C8051F960-B-GM Datasheet, PDF (327/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 25.7. PC0CTR0H: PC0 Counter 0 High (MSB)
Bit
7
6
5
4
3
2
1
0
Name
PC0CTR0H[23:16]
Type
R
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xDC; SFR Page = 0x2
Bit
Name
7:0 PC0CTR0H[23:16] PC0 Counter 0 High Byte
Bits 23:16 of Counter 0.
Function
SFR Definition 25.8. PC0CTR0M: PC0 Counter 0 Middle
Bit
7
6
5
4
3
2
1
0
Name
PC0CTR0M[15:8]
Type
R
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD8; SFR Page = 0x2
Bit
Name
7:0 PC0CTR0M[15:8] PC0 Counter 0 Middle Byte
Bits 15:8 of Counter 0.
Function
SFR Definition 25.9. PC0CTR0L: PC0 Counter 0 Low (LSB)
Bit
7
6
5
4
3
2
1
0
Name
PC0CTR0L[7:0]
Type
R
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xDA; SFR Page = 0x2
Bit
Name
7:0 PC0CTR0L[7:0] PC0 Counter 0 Low Byte
Bits 7:0 of Counter 0.
Function
Note: PC0CTR0L must be read before PC0CTR0M and PC0CTR0H to latch the count for reading. PC0CTRL must
be qualified using the RDVALID bit (PC0TH[0]).
Rev. 1.0
327