C8051F960-B-GM Datasheet, PDF (134/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
10.4. Multiplexed and Non-multiplexed Selection
The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode,
depending on the state of the EMD2 (EMI0CF.4) bit.
10.4.1. Multiplexed Configuration
In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins:
AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits
of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is
driven by the External Memory Interface logic. An example of a Multiplexed Configuration is shown in
Figure 10.1.
In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state
of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are pre-
sented to AD[7:0]. During this phase, the address latch is configured such that the Q outputs reflect the
states of the D inputs. When ALE falls, signaling the beginning of the second phase, the address latch out-
puts remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data
Bus controls the state of the AD[7:0] port at the time RD or WR is asserted.
See Section “10.6.2. Multiplexed Mode” on page 142 for more information.
A[15:8]
ADDRESS BUS
74HC373
E
ALE
G
AD[7:0] ADDRESS/DATA BUS D
Q
M
V_DD
I
(Optional)
8
F
WR
RD
A[15:8]
A[7:0]
64 K X 8
SRAM
I/O[7:0]
CE
WE
OE
Figure 10.1. Multiplexed Configuration Example
10.4.2. Non-multiplexed Configuration
In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-
multiplexed Configuration is shown in Figure 10.2. See Section “10.6.1. Non-Multiplexed Mode” on
page 139 for more information about Non-multiplexed operation.
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