C8051F960-B-GM Datasheet, PDF (296/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
24.1. SmaRTClock Interface
The SmaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These inter-
face registers are located on the CIP-51’s SFR map and provide access to the SmaRTClock internal regis-
ters listed in Table 24.1. The SmaRTClock internal registers can only be accessed indirectly through the
SmaRTClock Interface.
Table 24.1. SmaRTClock Internal Registers
SmaRTClock SmaRTClock
Address
Register
Register Name
0x00–0x03 CAPTUREn SmaRTClock Capture
Registers
Description
Four Registers used for setting the 32-bit
SmaRTClock timer or reading its current value.
0x04
0x05
0x06
0x07
0x08–0x0B
0x0C–0x0F
0x10–0x13
RTC0CN SmaRTClock Control
Register
Controls the operation of the SmaRTClock State
Machine.
RTC0XCN SmaRTClock Oscillator Controls the operation of the SmaRTClock
Control Register
Oscillator.
RTC0XCF
SmaRTClock Oscillator
Configuration Register
Controls the value of the progammable
oscillator load capacitance and
enables/disables AutoStep.
RTC0CF SmaRTClock
Contains an alarm enable and flag for each
Configuration Register SmaRTClock alarm.
ALARM0Bn SmaRTClock Alarm
Registers
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
ALARM1Bn SmaRTClock Alarm
Registers
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
ALARM2Bn SmaRTClock Alarm
Registers
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
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Rev. 1.0