Z8F1680SH020SG Datasheet, PDF (95/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
70
8.2.
Architecture
Figure 10 displays the interrupt controller block diagram.
Port Interrupts
Internal Interrupts
High
Priority
Medium
Priority
Vector
Priority
Mux
IRQ Request
Low
Priority
Figure 10. Interrupt Controller Block Diagram
8.3.
Operation
This section describes the operational aspects of the following functions.
Master Interrupt Enable: see page 70
Interrupt Vectors and Priority: see page 71
Interrupt Assertion: see page 71
Software Interrupt Assertion: see page 72
8.3.1. Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables interrupts. Interrupts are globally enabled by any of the following actions:
• Execution of an Enable Interrupt (EI) instruction
• Execution of an Interrupt Return (IRET) instruction
PS025015-1212
PRELIMINARY
Interrupt Controller