Z8F1680SH020SG Datasheet, PDF (54/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
29
Table 8. Register File Address Map (Continued)
Address (Hex) Register Description
FD2
Port A Input Data
FD3
Port A Output Data
Mnemonic Reset (Hex)¹ Page #
PAIN
XX
60
PAOUT
00
60
GPIO Port B
FD4
FD5
FD6
FD7
Port B Address
Port B Control
Port B Input Data
Port B Output Data
PBADDR
00
58
PBCTL
00
60
PBIN
XX
60
PBOUT
00
60
GPIO Port C
FD8
FD9
FDA
FDB
Port C Address
Port C Control
Port C Input Data
Port C Output Data
PCADDR
00
58
PCCTL
00
60
PCIN
XX
60
PCOUT
00
60
GPIO Port D
FDC
FDD
FDE
FDF
Port D Address
Port D Control
Port D Input Data
Port D Output Data
PDADDR
00
58
PDCTL
00
60
PDIN
XX
60
PDOUT
00
60
GPIO Port E
FE0
FE1
FE2
FE3
FE4–FEF
Port E Address
Port E Control
Port E Input Data
Port E Output Data
Reserved
PEADDR
00
58
PECTL
00
60
PEIN
XX
60
PEOUT
00
60
—
XX
Reset
FF0
Reset Status
RSTSTAT
XX
40
FF1
Reserved
—
XX
Notes:
1. XX=Undefined.
2. The Reserved space can be configured as General-Purpose Register File RAM depending on the user option bits
(see the User Option Bits chapter on page 277) and the on-chip PRAM size (see the Ordering Information chapter
on page 372). If the PRAM is programmed as General-Purpose Register File RAM on Reserved space, the start-
ing address always begins immediately after the end of General-Purpose Register File RAM.
PS025015-1212
PRELIMINARY
Register Map