Z8F1680SH020SG Datasheet, PDF (261/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
236
State Register. The software responds to the Not Acknowledge interrupt by setting the
stop bit and clearing the TXI bit. The I²C controller flushes the Transmit Data
Register, sends the stop condition on the bus and clears the stop and NCKI bits. The
transaction is complete and the following steps can be ignored.
16. The I²C controller sends a repeated start condition.
17. The I²C controller loads the I²C Shift Register with the contents of the I²C Data
Register (the third address transfer).
18. The I²C controller sends 11110b, followed by the two most-significant bits of the
slave read address and a 1 (Read).
19. The I²C slave sends an Acknowledge by pulling the SDA signal Low during the next
High period of SCL.
20. The I²C controller shifts in a byte of data from the slave.
21. The I²C controller asserts the Receive interrupt.
22. The software responds by reading the I²C Data Register. If the next data byte is to be
the final byte, the software must set the NAK bit of the I²C Control Register.
23. The I²C controller sends an Acknowledge or Not Acknowledge to the I²C Slave,
based on the value of the NAK bit.
24. If there are more bytes to transfer, the I²C controller returns to Step 18.
25. The I²C controller generates a NAK interrupt (the NCKI bit in the I2CISTAT
Register).
26. The software responds by setting the stop bit of the I²C Control Register.
27. A stop condition is sent to the I²C Slave.
17.2.6. Slave Transactions
The following sections describe Read and Write transactions to the I²C controller
configured for 7-bit and 10-bit Slave modes.
17.2.6.1. Slave Address Recognition
The following two slave address recognition options are supported; a description of each
follows.
• Slave 7-Bit Address Recognition Mode
• Slave 10-Bit Address Recognition Mode
Slave 7-Bit Address Recognition Mode. If IRM = 0 during the address phase and the
controller is configured for MASTER/SLAVE or SLAVE 7-bit address mode, the
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller