Z8F1680SH020SG Datasheet, PDF (266/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
241
d. Set IEN = 1 in the I²C Control Register. Set NAK = 0 in the I²C Control Register.
2. The Master initiates a transfer by sending the address byte. The SLAVE Mode I²C
controller finds an address match and detects that the R/W bit = 1 (read by the master
from the slave). The I²C controller acknowledges, indicating that it is ready to accept
the transaction. The SAM bit in the I2CISTAT Register is set to 1, causing an
interrupt. The RD bit is set to 1, indicating a Read from the slave.
3. The software responds to the interrupt by reading the I2CISTAT Register, thereby
clearing the SAM bit. Because RD = 1, the software responds by loading the first data
byte into the I2CDATA Register. The software sets the TXI bit in the I2CCTL
Register to enable transmit interrupts. When the master initiates the data transfer, the
I²C controller holds SCL Low until the software has written the first data byte to the
I2CDATA Register.
4. SCL is released and the first data byte is shifted out.
5. After the first bit of the first data byte has been transferred, the I²C controller sets the
TDRE bit, which asserts the transmit data interrupt.
6. The software responds to the transmit data interrupt (TDRE = 1) by loading the next
data byte into the I2CDATA Register, which clears TDRE.
7. After the data byte has been received by the master, the master transmits an
Acknowledge instruction (or Not Acknowledge instruction if this byte is the final data
byte).
8. The bus cycles through Step 5 to Step 7 until the final byte has been transferred. If the
software has not yet loaded the next data byte when the master brings SCL Low to
transfer the most significant data bit, the slave I²C controller holds SCL Low until the
Data Register has been written. When a Not Acknowledge instruction is received by
the slave, the I²C controller sets the NCKI bit in the I2CISTAT Register causing the
Not Acknowledge interrupt to be generated.
9. The software responds to the Not Acknowledge interrupt by clearing the TXI bit in the
I2CCTL Register and by asserting the FLUSH bit of the I2CCTL Register to empty
the Data Register.
10. When the Master has completed the final acknowledge cycle, it asserts a stop or restart
condition on the bus.
11. The Slave I²C controller asserts the stop/restart interrupt (set SPRS bit in I2CISTAT
Register).
12. The software responds to the stop/restart interrupt by reading the I2CISTAT Register,
which clears the SPRS bit.
17.2.6.8. Slave Transmit Transaction With 10-Bit Address
The data transfer format for a master reading data from a slave with 10-bit addressing is
displayed in Figure 50. The following procedure describes the I²C Master/Slave Control-
ler operating as a slave in 10-bit addressing mode, transmitting data to the bus master.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller