Z8F1680SH020SG Datasheet, PDF (354/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
329
LD 234H, #%01 ; Another Load (LD) instruction with two operands.
; The first operand, Extended Mode Register Address 234H,
; identifies the destination. The second operand, Immediate Data
; value 01H, is the source. The value 01H is written into the
; Register at address 234H.
27.2. Assembly Language Syntax
For proper instruction execution, eZ8 CPU assembly language syntax requires that the
operands be written as destination and source. After assembly, the object code usually has
the operands in the order source, destination, but ordering is opcode-dependent. The
following instruction examples illustrate the format of some basic assembly instructions
and the resulting object code produced by the assembler. You must follow this binary
format if you prefer manual program coding or intend to implement your own assembler.
Example 1. If the contents of registers 43H and 08H are added and the result is stored in
43H, the assembly syntax and resulting object code is as listed in Table 174.
Table 174. Assembly Language Syntax Example 1
Assembly Language Code
Object Code
ADD
04
43H,
08
08H (ADD dst, src)
43 (OPC src, dst)
Example 2. In general, when an instruction format requires an 8-bit register address, that
address can specify any register location in the range 0–255 or, using Escaped Mode
Addressing, a Working Register R0–R15. If the contents of Register 43H and Working
Register R8 are added and the result is stored in 43H, the assembly syntax and resulting
object code is as listed in Table 175.
Table 175. Assembly Language Syntax Example 2
Assembly Language Code
Object Code
ADD
04
43H,
E8
R8 (ADD dst, src)
43 (OPC src, dst)
The register file size varies depending on the device type. See the device-specific product
specification to determine the exact register file range available.
PS025015-1212
PRELIMINARY
eZ8 CPU Instruction Set