Z8F1680SH020SG Datasheet, PDF (391/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
366
29.4.1. General Purpose I/O Port Input Data Sample Timing
Figure 75 displays timing of the GPIO Port input sampling. The input value on a GPIO
port pin is sampled on the rising edge of the system clock. The Port value is available to
the eZ8 CPU on the second rising clock edge following the change of the Port value.
TCLK
System
Clock
Port Pin
Input Value
Port Value
Changes to 0
Port Input Data
Register Latch
Port Input Data
Read on Data Bus
0 Latched
Into Port Input
Data Register
Port Input Data Register
Value 0 Read
by eZ8
Figure 75. Port Input Sample Timing
Table 204. GPIO Port Input Timing
Parameter
T_{S_PORT}
T_{H_PORT}
T_SMR
Abbreviation
Port Input Transition to XIN Rise Setup Time (Not pictured)
XIN Rise to Port Input Transition Hold Time (Not pictured)
GPIO Port Pin Pulse Width to ensure Stop Mode Recovery
(for GPIO Port Pins enabled as SMR sources)
Delay (ns)
Min
Max
5
–
0
–
1 µs
PS025015-1212
PRELIMINARY
Electrical Characteristics