Z8F1680SH020SG Datasheet, PDF (185/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
160
12.1.12. LIN-UART Baud Rate Generator
The LIN-UART Baud Rate Generator creates a lower frequency baud rate clock for data
transmission. The input to the Baud Rate Generator is the system clock. The LIN-UART
Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value
(BRG[15:0]) that sets the data-transmission rate (baud rate) of the LIN-UART. The LIN-
UART data rate for normal UART operation is calculated using the following equation:
UART Data Rate (bits/s) =
System Clock Frequency (Hz)
16 x UART Baud Rate Divisor Value
The LIN-UART data rate for LIN mode UART operation is calculated using the following
equation:
System Clock Frequency (Hz)
UART Data Rate (bits/s) =
UART Baud Rate Divisor Value
When the LIN-UART is disabled, the BRG functions as a basic 16-bit timer with interrupt
on time-out. To configure the BRG as a timer with interrupt on time-out, follow the proce-
dure below:
1. Disable the LIN-UART receiver by clearing the REN bit in the LIN-UART Control 0
Register to 0 (i.e., the TEN bit can be asserted; transmit activity can occur).
2. Load the appropriate 16-bit count value into the LIN-UART Baud Rate High and Low
Byte registers.
3. Enable the BRG timer function and the associated interrupt by setting the BRGCTL
bit in the LIN-UART Control 1 Register to 1.
12.2. Noise Filter
A noise filter circuit is included which filters noise on a digital input signal (such as UART
Receive Data) before the data is sampled by the block. This noise filter is likely to be a
requirement for protocols with a noisy environment.
The noise filter contains the following features:
• Synchronizes the receive input data to the System Clock
• Noise Filter Enable (NFEN) input selects whether the noise filter is bypassed (NFEN
= 0) or included (NFEN = 1) in the receive data path
PS025015-1212
PRELIMINARY
LIN-UART