Z8F1680SH020SG Datasheet, PDF (58/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
33
On Reset, control registers within the Register File that have a defined Reset value are
loaded with their Reset values. Other control registers (including the Stack Pointer,
Register Pointer and Flags) and general-purpose RAM are not initialized and undefined
following Reset. The eZ8 CPU fetches the Reset vector at Program Memory addresses
0002H and 0003H and loads that value into the Program Counter. Program execution
begins at the Reset vector address.
Because the control registers are reinitialized by a System Reset, the system clock after
reset is always the 11 MHz IPO. User software must reconfigure the oscillator control
block such that the correct system clock source is enabled and selected.
5.2.
Reset Sources
Table 10 lists the possible sources of a System Reset.
Operating Mode
NORMAL or 
HALT Mode
STOP Mode
Table 10. Reset Sources and Resulting Reset Type
Reset Source
Special Conditions
Power-On Reset
Reset delay begins after supply voltage
exceeds POR level
Voltage Brown-Out
Reset delay begins after supply voltage
exceeds VBO level
Watchdog Timer time-out
when configured for Reset
None
RESET pin assertion
All reset pulses less than three system clocks
in width are ignored, see the Electrical
Characteristics chapter on page 349.
On-Chip Debugger initiated Reset System Reset, except the OCD is unaffected
(OCDCTL[0] set to 1)
by reset
Power-On Reset
Reset delay begins after supply voltage
exceeds POR level
Voltage Brown-Out
Reset delay begins after supply voltage
exceeds VBO level
RESET pin assertion
All reset pulses less than the specified analog
delay is ignored, see the Electrical
Characteristics chapter on page 349.
DBG pin driven Low
None
PS025015-1212
P R E L I M I N A R Y Reset, Stop Mode Recovery and Low-Voltage