Z8F1680SH020SG Datasheet, PDF (65/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
40
writing this bit does not clear it. The LVD circuit can also generate an interrupt when
enabled (see the Interrupt Vectors and Priority section on page 71). The LVD is not
latched, so enabling the interrupt is the only way to guarantee detection of a transient low-
voltage event.
The LVD circuit is either enabled or disabled by the Power Control Register bit 4. For
more details, see the Power Control Register Definitions section on page 44.
5.5. Reset Register Definitions
The following sections define the Reset registers.
5.5.0.1. Reset Status Register
The Reset Status (RSTSTAT) Register, shown in Table 12, is a read-only register that indi-
cates the source of the most recent Reset event, Stop Mode Recovery event and/or WDT
time-out. Reading this register resets the upper 4 bits to 0.
This register shares its address with the Reset Status Register, which is write-only.
Table 12. Reset Status Register (RSTSTAT)
Bits
7
6
5
4
3
2
1
0
Field
POR/VBO STOP
WDT
EXT
Reserved
LVD
Reset
See Table 13
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
FF0H
Bit
[7]
POR/VBO
[6]
STOP
[5]
WDT
Description
Power-On initiated VBO Reset or general VBO Reset Indicator
If this bit is set to 1, a POR or VBO Reset event occurs. This bit is reset to 0, if a WDT time-
out or Stop Mode Recovery occurs. This bit is also reset to 0 when the register is read.
Stop Mode Recovery Indicator
If this bit is set to 1, a Stop Mode Recovery occurs. If the STOP and WDT bits are both set
to 1, the Stop Mode Recovery occurs because of a WDT time-out. If the stop bit is 1 and the
WDT bit is 0, the Stop Mode Recovery is not caused by a WDT time-out. This bit is reset by
Power-On Reset or WDT time-out that occurred while not in STOP Mode. Reading this
register also resets this bit.
Watchdog Timer time-out Indicator
If this bit is set to 1, a WDT time-out occurs. A POR resets this pin. A Stop Mode Recovery
from a change in an input pin also resets this bit. Reading this register resets this bit. This
Read must occur before clearing the WDT interrupt.
PS025015-1212
P R E L I M I N A R Y Reset, Stop Mode Recovery and Low-Voltage