Z8F1680SH020SG Datasheet, PDF (183/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
158
Note: In MULTIPROCESSOR Mode (MPEN=1), the receive-data interrupts are dependent on
the multiprocessor configuration and the most recent address byte.
• A break is received
• A Receive Data Overrun or LIN Slave Autobaud Overrun Error is detected
• A Data Framing Error is detected
• A Parity Error is detected (physical layer error in LIN mode)
12.1.11.3. LIN-UART Overrun Errors
When an overrun error condition occurs, the LIN-UART prevents overwriting of the valid
data currently in the Receive Data Register. The Break Detect and Overrun status bits are
not displayed until after the valid data has been read.
After the valid data has been read, the OE bit of the Status 0 register is updated to indicate
the overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate
that the Receive Data Register contains a data byte. However, because the overrun error
occurred, this byte cannot contain valid data and must be ignored. The BRKD bit indicates
if the overrun is caused by a break condition on the line. After reading the status byte indi-
cating an overrun error, the Receive Data Register must be read again to clear the error bits
in the LIN-UART Status 0 Register.
In LIN mode, an Overrun Error is signalled for receive-data overruns as described above
and in the LIN Slave if the BRG Counter overflows during the autobaud sequence (the
ATB bit will also be set in this case). There is no data associated with the autobaud over-
flow interrupt; however the Receive Data Register must be read to clear the OE bit. In this
case, software must write a 10B to the LinState field, forcing the LIN slave back to a Wait
for Break state.
12.1.11.4. LIN-UART Data- and Error-Handling Procedure
Figures 24 displays the recommended procedure for use in LIN-UART receiver interrupt
service routines.
PS025015-1212
PRELIMINARY
LIN-UART