Z8F1680SH020SG Datasheet, PDF (49/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
24
Table 8. Register File Address Map (Continued)
Address (Hex) Register Description
F20
Timer 0 PWM1 High Byte
Mnemonic Reset (Hex)¹ Page #
T0PWM1H
00
111
F21
Timer 0 PWM1 Low Byte
T0PWM1L
00
111
F22
Timer 0 Control 2
F23
Timer 0 Status
T0CTL2
00
117
T0STA
00
118
F2C
Timer 0 Noise Filter Control
T0NFC
00
119
Timer 1
F08
Timer 1 High Byte
T1H
00
109
F09
Timer 1 Low Byte
F0A
Timer 1 Reload High Byte
T1L
T1RH
01
109
FF
110
F0B
Timer 1 Reload Low Byte
F0C
Timer 1 PWM0 High Byte
T1RL
FF
110
T1PWM0H
00
110
F0D
Timer 1 PWM0 Low Byte
T1PWM0L
00
111
F0E
Timer 1 Control 0
F0F
Timer 1 Control 1
T1CTL0
00
112
T1CTL1
00
113
F24
Timer 1 PWM1 High Byte
T1PWM1H
00
111
F25
Timer 1 PWM1 Low Byte
F26
Timer 1 Control 2
T1PWM1L
00
111
T1CTL2
00
117
F27
Timer 1 Status
F2D
Timer 1 Noise Filter Control
T1STA
T1NFC
00
118
00
119
Timer 2
F10
Timer 2 High Byte
F11
Timer 2 Low Byte
T2H
00
109
T2L
01
110
F12
Timer 2 Reload High Byte
F13
Timer 2 Reload Low Byte
T2RH
T2RL
FF
110
FF
110
F14
Timer 2 PWM0 High Byte
T2PWM0H
00
110
F15
Timer 2 PWM0 Low Byte
F16
Timer 2 Control 0
T2PWM0L
00
111
T2CTL0
00
112
Notes:
1. XX=Undefined.
2. The Reserved space can be configured as General-Purpose Register File RAM depending on the user option bits
(see the User Option Bits chapter on page 277) and the on-chip PRAM size (see the Ordering Information chapter
on page 372). If the PRAM is programmed as General-Purpose Register File RAM on Reserved space, the start-
ing address always begins immediately after the end of General-Purpose Register File RAM.
PS025015-1212
PRELIMINARY
Register Map