Z8F1680SH020SG Datasheet, PDF (163/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
138
Bit
[5]
CHIEN
[4]
CHUE
[3]
[2:0]
CHOP
Description (Continued)
Channel Interrupt Enable
This bit enables generation of channel interrupt. A channel interrupt is generated whenever
there is a capture/compare event on the Timer Channel.
0 = Channel interrupt is disabled.
1 = Channel interrupt is enabled.
Channel Update Enable
This bit determines whether writes to the Channel High and Low Byte registers are buffered
when TEN = 1. Writes to these registers are not buffered when TEN = 0 regardless of the value
of this bit.
0 = Writes to the Channel High and Low Byte registers are buffered when TEN = 1 and only
take affect on the next end of cycle count.
1 = Writes to the Channel High and Low Byte registers are not buffered when TEN = 1.
Reserved; must be 0.
Channel Operation Method
This field determines the operating mode of the channel. For a detailed description of the
operating modes, see Count Up/Down Mode on page 123.
000 = One-Shot Compare operation.
001 = Continuous Compare operation.
010 = PWM Output operation.
011 = Capture operation.
100 – 111 = Reserved.
PS025015-1212
PRELIMINARY
Multi-Channel Timer