Z8F1680SH020SG Datasheet, PDF (180/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
155
UART Control 0 Register must be initialized with TEN = 1, REN = 1 and all other bits =
0.
In addition to the LMST, LSLV and ABEN bits in the LIN Control Register, a
LinState[1:0] field exists which defines the current state of the LIN logic. This field is
initially set by software. In the LIN SLAVE Mode, the LinState field is updated by
hardware as the slave moves through the Wait For Break, AutoBaud and Active states.
12.1.10.3. LIN MASTER Mode Operation
LIN MASTER Mode is selected by setting LMST = 1, LSLV = 0, ABEN = 0 and Lin-
State[1:0] = 11B. If the LIN bus protocol indicates the bus is required go into the LIN
SLEEP state, the LinState[1:0] bits must be set to 00B by software.
The break is the first part of the message frame transmitted by the master, consisting of at
least 13 bit periods of logical zero on the LIN bus. During initialization of the LIN master,
the duration (in bit times) of the break is written to the TxBreakLength field of the LIN
Control Register. The transmission of the break is performed by setting the SBRK bit in
the Control 0 Register. The LIN-UART starts the break after the SBRK bit is set and any
character transmission currently underway has completed. The SBRK bit is deasserted by
hardware until the break is completed.
If it is necessary to generate a break longer than 15 bit times, the SBRK bit can be used in
normal UART mode where software times the duration of the break.
The Synch character is transmitted by writing a 55H to the Transmit Data Register (TDRE
must = 1 before writing). The Synch character is not transmitted by the hardware until the
break is complete.
The identifier character is transmitted by writing the appropriate value to the Transmit
Data Register (TDRE must = 1 before writing).
If the master is sending the response portion of the message, these data and checksum
characters are written to the Transmit Data Register when the TDRE bit asserts. If the
Transmit Data Register is written after TDRE asserts, but before TXE asserts, the
hardware inserts one or two stop bits between each character as determined by the stop bit
in the Control 0 Register. Additional idle time occurs between characters, if TXE asserts
before the next character is written.
If the selected slave is sending the response portion of the frame to the master, each
receive byte will be signalled by the receive data interrupt (RDA bit will be set in the Sta-
tus 0 Register). If the selected slave is sending the response to a different slave, the master
can ignore the response characters by deasserting the REN bit in the Control 0 Register
until the frame time slot is completed.
12.1.10.4. LIN SLEEP Mode
While the LIN bus is in the sleep state, the CPU can either be in low power STOP Mode,
in HALT Mode, or in normal operational state. Any device on the LIN bus can issue a
PS025015-1212
PRELIMINARY
LIN-UART