Z8F1680SH020SG Datasheet, PDF (125/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
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9.2.3.10. COMPARE Mode
In COMPARE Mode, the timer counts up to the 16-bit maximum Compare value stored in
the Timer Reload High and Low Byte registers. The Timer counts timer clocks up to a 16-
bit reload value. Upon reaching the Compare value, the timer generates an interrupt and
counting continues (the timer value is not reset to 0001H). Also, if the Timer Output
alternate function is enabled, the Timer Output pin changes state (from Low to High or
from High to Low) on Compare.
If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting.
Observe the following steps to configure a timer for COMPARE Mode and initiate the
count:
1. Write to the Timer Control 1 Register to:
– Disable the timer
– Configure the timer for COMPARE Mode
– Set the prescale valu.
– Set the initial logic level (High or Low) for the Timer Output alternate function, if
required
2. Write to the Timer Control 2 Register to choose the timer clock source.
3. Write to the Timer Control 0 Register to set the timer interrupt configuration field
TICONFIG.
4. Write to the Timer High and Low Byte registers to set the starting count value.
5. Write to the Timer Reload High and Low Byte registers to set the Compare value.
6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
7. When using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
8. Write to the Timer Control 1 Register to enable the timer and initiate counting.
In COMPARE Mode, the timer clock always provides the timer input. The Compare time
is calculated using the following equation:
9.2.3.11. GATED Mode
In GATED Mode, the timer counts only when the Timer Input signal is in its active state
(asserted) as determined by the TPOL bit in the Timer Control 1 Register. When the Timer
Input signal is asserted, counting begins. A Timer Interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
PS025015-1212
PRELIMINARY
Timers