Z8F1680SH020SG Datasheet, PDF (107/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
82
8.4.7. Interrupt Edge Select Register
Bits
Field
Reset
R/W
Address
The Interrupt Edge Select (IRQES) Register, shown in Table 49, determines whether an
interrupt is generated for the rising edge or falling edge on the selected GPIO Port A or
Port D input pin.
Table 49. Interrupt Edge Select Register (IRQES)
7
IES7
0
R/W
6
IES6
0
R/W
5
IES5
0
R/W
4
3
IES4
IES3
0
0
R/W
R/W
FCDH
2
IES2
0
R/W
1
IES1
0
R/W
0
IES0
0
R/W
Bit
[7:0]
IESx
Description
Interrupt Edge Select x
0 = An interrupt request is generated on the falling edge of the PAx input or PDx input.
1 = An interrupt request is generated on the rising edge of the PAx input or PDx input; x
indicates the specific GPIO port pin number (0–7).
8.4.8. Shared Interrupt Select Register
The Shared Interrupt Select (IRQSS) Register, shown in Table 50, determines the source
of the PADxS interrupts. The Shared Interrupt Select Register selects between Port A and
alternate sources for the individual interrupts.
Table 50. Shared Interrupt Select Register (IRQSS)
Bits
Field
Reset
R/W
Address
7
PA7VS
0
R/W
6
PA6CS
0
R/W
5
PA5CS
0
R/W
4
3
PAD4S PAD3S
0
0
R/W
R/W
FCEH
2
PAD2S
0
R/W
1
PAD1S
0
R/W
0
Reserved
0
R/W
Bit
[7]
PA7VS
[6]
PA6CS
Description
PA7/LVD Selection
0 = PA7 is used for the interrupt for PA7VS interrupt request.
1 = The LVD is used for the interrupt for PA7VS interrupt request.
PA6/Comparator 0 Selection
0 = PA6 is used for the interrupt for PA6CS interrupt request.
1 = The Comparator 0 is used for the interrupt for PA6CS interrupt request.
PS025015-1212
PRELIMINARY
Interrupt Controller