Z8F1680SH020SG Datasheet, PDF (179/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
154
In LIN mode, the interrupts defined for normal UART operation still apply with the
following changes:
• A Parity Error (the PE bit in the Status 0 Register) is redefined as the Physical Layer
Error (PLE) bit. The PLE bit indicates that receive data does not match transmit data
when the LIN-UART is transmitting. This definition applies to both Master and Slave
operating modes.
• The Break Detect interrupt (BRKD bit in Status 0 Register) indicates when a Break is
detected by the slave (break condition for at least 11 bit times). Software can use this
interrupt to start a timer checking for message frame time-out. The duration of the
break can be read in the RxBreakLength[3:0] field of the Mode Select and Status Reg-
ister.
• The Break Detect interrupt (BRKD bit in Status 0 Register) indicates when a wake-up
message has been received, if the LIN-UART is in LIN SLEEP state.
• In LIN SLAVE Mode, if the BRG counter overflows while measuring the autobaud pe-
riod (from the start bit to the beginning of bit 7 of the autobaud character), an Overrun
Error is indicated (OE bit in the Status 0 Register). In this case, software sets the LIN-
STATE field back to 10b, where the slave ignores the current message and waits for
the next break. The Baud Reload High and Low registers are not updated by hardware
if this autobaud error occurs. The OE bit is also set if a data overrun error occurs.
12.1.10.1. LIN System Clock Requirements
The LIN Master provides the timing reference for the LIN network and is required to have
a clock source with a tolerance of ±0.5%. A slave with autobaud capability is required to
have a baud clock matching the master oscillator within ±14%. The slave nodes autobaud
to lock onto the master timing reference with an accuracy of ±2%. If a slave does not
contain autobaud capability, it must include a baud clock which deviates from the masters
by not more than ±1.5%. These accuracy requirements must include the effects such as
voltage and temperature drift during operation.
Before sending/receiving messages, the Baud Reload High/Low registers must be
initialized. Unlike standard UART modes, the Baud Reload High/Low registers must be
loaded with the baud interval rather than 1/16 of the baud interval.
In order to autobaud with the required accuracy, the LIN SLAVE system clock must be at
least 100 times the baud rate.
12.1.10.2. LIN Mode Initialization and Operation
The LIN protocol mode is selected by setting either the LIN Master (LMST) or LIN
SLAVE (LSLV) and optionally (for the LIN SLAVE) the Autobaud Enable (ABEN) bits
in the LIN Control Register. To access the LIN Control Register, the Mode Select (MSEL)
field of the LIN-UART Mode Select/Status Register must be equal to 010B. The LIN-
PS025015-1212
PRELIMINARY
LIN-UART