Z8F1680SH020SG Datasheet, PDF (222/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
197
Chapter 16. Enhanced Serial Peripheral
Interface
The Enhanced Serial Peripheral Interface (ESPI) supports the Serial Peripheral Interface
(SPI) and other synchronous serial interface modes, such as Inter-IC Sound (I²S) and time
division multiplexing (TDM). ESPI includes the following features:
• Full-duplex, synchronous, character-oriented communication
• Four-wire interface (SS, SCK, MOSI and MISO)
• Data Shift Register is buffered to enable high throughput
• MASTER Mode transfer rates up to a maximum of one-half the system clock
frequency
• SLAVE Mode transfer rates up to a maximum of one-eighth the system clock
frequency
• Error detection
• Dedicated Programmable Baud Rate Generator
• Data transfer control via polling, interrupt
16.1. Architecture
The ESPI is a full-duplex, synchronous, character-oriented channel that supports a four-
wire interface (serial clock, transmit data, receive data and slave select). The ESPI block
consists of a shift register, data buffer register, a Baud Rate (clock) Generator, control/
status registers and a control state machine. Transmit and receive transfers are in synch as
there is a single shift register for both transmitting and receiving data. Figure 33 displays a
diagram of the ESPI block.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface