Z8F1680SH020SG Datasheet, PDF (210/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
185
The window remains open until the count again reaches 8 (in other words, 24 baud clock
periods since the previous pulse is detected), giving the endec a sampling window of
minus 4 baud rate clocks to plus 8 baud rate clocks around the expected time of an
incoming pulse. If an incoming pulse is detected inside this window this process is
repeated. If the incoming data is a logical 1 (no pulse), the endec returns to the initial state
and waits for the next falling edge. As each falling edge is detected, the endec clock
counter is reset, resynchronizing the endec to the incoming signal, allowing the endec to
tolerate jitter and baud rate errors in the incoming datastream. Resynchronizing the endec
does not alter the operation of the UART, which ultimately receives the data. The UART is
only synchronized to the incoming data stream when a start bit is received.
13.3. Infrared Encoder/Decoder Control Register
Definitions
All infrared endec configuration and status information is set by the UART control
registers as defined beginning on page 163.
Caution: _{To prevent spurious signals during IrDA data transmission, set the IREN bit in the}
UART Control 1 Register to 1 to enable the infrared encoder/decoder before enabling
the GPIO Port alternate function for the corresponding pin of UART. See Tables 17
through 19 on pages 49–54 for details.
PS025015-1212
PRELIMINARY
Infrared Encoder/Decoder