Z8F1680SH020SG Datasheet, PDF (262/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
237
hardware detects a match to the 7-bit slave address defined in the I2CSLVAD Register and
generates the slave address match interrupt (the SAM bit = 1 in the I2CISTAT Register).
The I²C controller automatically responds during the Acknowledge phase with the value
in the NAK bit of the I2CCTL Register.
Slave 10-Bit Address Recognition Mode. If IRM = 0 during the address phase and the
controller is configured for MASTER/SLAVE or SLAVE 10-bit address mode, the
hardware detects a match to the 10-bit slave address defined in the I2CMODE and
I2CSLVAD registers and generates the slave address match interrupt (the SAM bit = 1 in
the I2CISTAT Register). The I²C controller automatically responds during the
Acknowledge phase with the value in the NAK bit of the I2CCTL Register.
17.2.6.2. General Call and Start Byte Address Recognition
If GCE = 1 and IRM = 0 during the address phase and the controller is configured for
MASTER/SLAVE or SLAVE in either 7- or 10-bit address modes, the hardware detects a
match to the General Call Address or the start byte and generates the slave address match
interrupt. A General Call Address is a 7-bit address of all 0’s with the R/W bit = 0. A start
byte is a 7-bit address of all 0’s with the R/W bit = 1. The SAM and GCA bits are set in the
I2CISTAT Register. The RD bit in the I2CISTAT Register distinguishes a General Call
Address from a start byte which is cleared to 0 for a General Call Address). For a General
Call Address, the I²C controller automatically responds during the address acknowledge
phase with the value in the NAK bit of the I2CCTL Register. If the software is set to pro-
cess the data bytes associated with the GCA bit, the IRM bit can optionally be set follow-
ing the SAM interrupt to allow the software to examine each received data byte before
deciding to set or clear the NAK bit. A start byte will not be acknowledged—a require-
ment of the I²C specification.
17.2.6.3. Software Address Recognition
To disable hardware address recognition, the IRM bit must be set to 1 prior to the
reception of the address byte(s). When IRM = 1, each received byte generates a receive
interrupt (RDRF = 1 in the I2CISTAT Register). The software must examine each byte and
determine whether to set or clear the NAK bit. The slave holds SCL Low during the
Acknowledge phase until the software responds by writing to the I2CCTL Register. The
value written to the NAK bit is used by the controller to drive the I²C bus, then releasing
the SCL. The SAM and GCA bits are not set when IRM = 1 during the address phase, but
the RD bit is updated based on the first address byte.
17.2.6.4. Slave Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate data transferred from
the Master to the Slave and the unshaded regions indicate the data transferred from the
Slave to the Master. The transaction field labels are defined as follows:
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller