Z8F1680SH020SG Datasheet, PDF (199/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
174
12.3.7. Noise Filter Control Register
When MSEL = 001b, the Noise Filter Control Register, shown in Table 91, provides con-
trol for the digital noise filter.
Table 91. Noise Filter Control Register (U0CTL1 = F43H with MSEL = 001b)
Bit
7
6
5
4
3
2
1
0
Field
NFEN
NFCTL
—
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R
R
R
Address
F43H, F4BH
Note: R = Read; R/W = Read/Write.
Bit Position
[7]
NFEN
[6:4]
NFCTL
[3:0]
Reserved
Value Description
Noise Filter Enable
0
Noise filter is disabled.
1
Noise filter is enabled. Receive data is preprocessed by the noise filter.
Noise Filter Control
This field controls the delay and noise rejection characteristics of the noise filter. The
wider the counter is, the more delay is introduced by the filter and the wider the noise
event is filtered.
000 4-bit up/down counter.
001 5-bit up/down counter.
010 6-bit up/down counter.
011 7-bit up/down counter.
100 8-bit up/down counter.
101 9-bit up/down counter.
110 10-bit up/down counter.
111 11-bit up/down counter.
—
Reserved; must be 0000.
PS025015-1212
PRELIMINARY
LIN-UART