Z8F1680SH020SG Datasheet, PDF (195/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
170
12.3.5. LIN-UART Control 0 Register
The LIN-UART Control 0 Register, shown in Table 89, configures the basic properties of
LIN-UART’s transmit and receive operations. A more detailed discussion of each bit
follows the table.
Table 89. LIN-UART Control 0 Register (U0CTL0 = F42H)
Bit
7
Field
TEN
Reset
0
R/W
R/W
Address
Note: R/W = Read/Write.
6
REN
0
R/W
5
CTSE
0
R/W
4
3
PEN
PSEL
0
0
R/W
R/W
F42H, F4AH
2
SBRK
0
R/W
1
STOP
0
R/W
0
LBEN
0
R/W
Bit
[7]
TEN
[6]
REN
[5]
CTSE
[4]
PEN
[3]
PSEL
Description
Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is Low and the CTSE bit is 1, the transmitter is enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
Clear To Send Enable
0 = The CTS signal has no effect on the transmitter.
1 = The LIN-UART recognizes the CTS signal as an enable control for the transmitter.
Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit.
0 = Parity is disabled. This bit is overridden by the MPEN bit.
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit.
Parity Select
0 = Even parity is sent as an additional parity bit for the transmitter/receiver.
1 = Odd parity is sent as an additional parity bit for the transmitter/receiver.
PS025015-1212
PRELIMINARY
LIN-UART