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Z8F1680SH020SG Datasheet, PDF (276/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers
Z8 Encore! XP® F1680 Series
Product Specification
251
Bits
Field
Reset
R/W
Address
Table 125. I2C State Register (I2CSTATE)—Description when DIAG = 0
7
6
5
ACKV
ACK
AS
0
0
0
R
R
R
4
3
DS
10B
0
0
R
R
F55H
2
RSTR
0
R
1
SCLOUT
1
R
0
BUSY
0
R
Bit
Description
[7]
ACKV
ACK Valid
This bit is set, if sending data (Master or Slave) and the ACK bit in this register is valid for the
byte just transmitted. This bit can be monitored if it is appropriate for software to verify the ACK
value before writing the next byte to be sent. To operate in this mode, the Data Register must
not be written when TDRE asserts; instead, the software waits for ACKV to assert. This bit
clears when transmission of the next byte begins or the transaction is ended by a stop or
restart condition.
[6]
ACK
Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received. This
bit is set for an Acknowledge and cleared for a Not Acknowledge condition.
[5]
Address State
AS
This bit is active High while the address is being transferred on the I2C bus.
[4]
Data State
DS
This bit is active High while the data is being transferred on the I2C bus.
[3]
10B
10B
This bit indicates whether a 7-bit or 10-bit address is being transmitted when operating as a
Master. After the start bit is set, if the five most-significant bits of the address are 11110B, this
bit is set. When set, it is Reset after the address has been sent.
[2]
RSTR
RESTART
This bit is updated each time a stop or restart interrupt occurs (SPRS bit set in I2CISTAT
Register).
0 = Stop condition.
1 = Restart condition.
[1]
Serial Clock Output
SCLOUT Current value of Serial Clock being output onto the bus. The actual values of the SCL and SDA
signals on the I2C bus can be observed via the GPIO Input Register.
[0]
BUSY
I2C Bus Busy
0 = No activity on the I2C Bus.
1 = A transaction is underway on the I2C bus.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller