Z8F1680SH020SG Datasheet, PDF (144/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
119
9.3.7. Timer 0–2 Noise Filter Control Register
The Timer 0–2 Noise Filter Control Register (TxNFC) enables and disables the Timer
Noise Filter and sets the noise filter control.
Table 67. Timer 0–2 Noise Filter Control Register (TxNFC)
Bit
7
6
5
4
3
2
1
0
Field
NFEN
NFCTL
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
Address
F2CH, F2DH, F2EH
Bit
[7]
NFEN
[6:4]
NFCTL
[3:0]
Description
Noise Filter Enable
0 = Noise Filter is disabled.
1 = Noise Filter is enabled. Receive data is preprocessed by the noise filter.
Noise Filter Control
This field controls the delay and noise rejection characteristics of the Noise Filter. The wider
the counter the more delay that is introduced by the filter and the wider the noise event that will
be filtered.
000 = 2-bit up/down counter
001 = 3-bit up/down counter
010 = 4-bit up/down counter
011 = 5-bit up/down counter
100 = 6-bit up/down counter
101 = 7-bit up/down counter
110 = 8-bit up/down counter
111 = 9-bit up/down counter
Reserved; must be 0.
PS025015-1212
PRELIMINARY
Timers