Z8F1680SH020SG Datasheet, PDF (253/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
228
17.2.3. Start and Stop Conditions
The Master generates the start and stop conditions to start or end a transaction. To start a
transaction, the I²C controller generates a start condition by pulling the SDA signal Low
while SCL is High. To complete a transaction, the I²C controller generates a stop
condition by creating a Low-to-High transition of the SDA signal while the SCL signal is
High. These start and stop events occur when the start and stop bits in the I²C Control
Register are written by software to begin or end a transaction. Any byte transfer currently
under way including the Acknowledge phase finishes before the start or stop condition
occurs.
17.2.4. Software Control of I²C Transactions
The I²C controller is configured via the I²C Control and I²C Mode registers. The
MODE[1:0] field of the I²C Mode Register allows the configuration of the I²C controller
for MASTER/SLAVE or SLAVE ONLY mode and configures the slave for 7-bit or 10-bit
addressing recognition.
MASTER/SLAVE Mode can be used for:
• MASTER ONLY operation in a Single Master/One or More Slave I²C system
• MASTER/SLAVE in a Multimaster/multislave I²C system
• SLAVE ONLY operation in an I²C system
In SLAVE ONLY mode, the start bit of the I²C Control Register is ignored (software can-
not initiate a master transaction by accident) and operation to SLAVE ONLY Mode is
restricted thereby preventing accidental operation in MASTER Mode. The software con-
trols I²C transactions by enabling the I²C controller interrupt in the interrupt controller or
by polling the I²C Status Register.
To use interrupts, the I²C interrupt must be enabled in the interrupt controller and followed
by executing an EI instruction. The TXI bit in the I²C Control Register must be set to
enable transmit interrupts. An I²C interrupt service routine then checks the I²C Status
Register to determine the cause of the interrupt.
To control transactions by polling, the TDRE, RDRF, SAM, ARBLST, SPRS and NCKI
interrupt bits in the I²C Status Register should be polled. The TDRE bit asserts regardless
of the state of the TXI bit.
17.2.5. Master Transactions
The following sections describe Master Read and Write transactions to both 7-bit and 10-
bit slaves.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller