Z8F1680SH020SG Datasheet, PDF (55/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
30
Table 8. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic Reset (Hex)¹ Page #
Watchdog Timer
FF2
Watchdog Timer Reload High Byte
FF3
Watchdog Timer Reload Low Byte
FF4–FF5
Reserved
WDTH
WDTL
—
FF
143
FF
143
XX
Trim Bit Control
FF6
Trim Bit Address
FF7
Trim Data
TRMADR
00
281
TRMDR
XX
281
Flash Memory Controller
FF8
Flash Control
Flash Status
FF9
Flash Page Select
Flash Sector Protect
FFA
Flash Programming Frequency High Byte
FFB
Flash Programming Frequency Low Byte
FCTL
00
272
FSTAT
00
272
FPS
00
273
FPROT
00
274
FFREQH
00
275
FFREQL
00
275
eZ8 CPU
FFC
Flags
FFD
Register Pointer
FFE
Stack Pointer High Byte
FFF
Stack Pointer Low Byte
—
RP
SPH
SPL
XX
refer to
XX
the eZ8
CPU
XX
Core
XX
User
Manual
(UM0128)
Notes:
1. XX=Undefined.
2. The Reserved space can be configured as General-Purpose Register File RAM depending on the user option bits
(see the User Option Bits chapter on page 277) and the on-chip PRAM size (see the Ordering Information chapter
on page 372). If the PRAM is programmed as General-Purpose Register File RAM on Reserved space, the start-
ing address always begins immediately after the end of General-Purpose Register File RAM.
PS025015-1212
PRELIMINARY
Register Map