Z8F1680SH020SG Datasheet, PDF (264/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
239
5. The I²C controller receives the data byte and responds with Acknowledge or Not
Acknowledge depending on the state of the NAK bit in the I2CCTL Register. The I²C
controller generates the receive data interrupt by setting the RDRF bit in the
I2CISTAT Register.
6. The software responds by reading the I2CISTAT Register, finding the RDRF bit = 1
and reading the I2CDATA Register clearing the RDRF bit. If software can accept only
one more data byte it sets the NAK bit in the I2CCTL Register.
7. The master and slave loops through Step 4 to Step 6 until the master detects a Not
Acknowledge instruction or runs out of data to send.
8. The master sends the stop or restart signal on the bus. Either of these signals can cause
the I²C controller to assert a stop interrupt (the stop bit = 1 in the I2CISTAT Register).
Because the slave received data from the master, the software takes no action in
response to the stop interrupt other than reading the I2CISTAT Register to clear the
stop bit in the I2CISTAT Register.
17.2.6.6. Slave Receive Transaction with 10-Bit Address
The data transfer format for writing data from a master to a slave with 10-bit addressing is
displayed in Figure 48. The procedure that follows describes the I²C Master/Slave Con-
troller operating as a slave in 10-bit addressing mode and receiving data from the bus mas-
ter.
s
S
Slave Address
1st Byte
W=0
A
Slave Address
2nd Byte
A
Data
A
Data A/A P/S
Figure 48. Data Transfer Format—Slave Receive Transaction with 10-Bit Address
1. The software configures the controller for operation as a slave in 10-bit addressing
mode, as follows:
a. Initialize the MODE field in the I2CMODE Register for either SLAVE ONLY
mode or MASTER/SLAVE Mode with 10-bit addressing.
b. Optionally set the GCE bit.
c. Initialize the SLA[7:0] bits in the I2CSLVAD Register and the SLA[9:8] bits in
the I2CMODE Register.
d. Set IEN = 1 in the I2CCTL Register. Set NAK = 0 in the I²C Control Register.
2. The Master initiates a transfer, sending the first address byte. The I²C controller rec-
ognizes the start of a 10-bit address with a match to SLA[9:8] and detects R/W bit = 0
(a Write from the master to the slave). The I²C controller acknowledges, indicating it
is available to accept the transaction.
3. The Master sends the second address byte. The SLAVE Mode I²C controller detects
an address match between the second address byte and SLA[7:0]. The SAM bit in the
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller