Z8F1680SH020SG Datasheet, PDF (337/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
312
23.4.2. OCD Status Register
The OCD Status Register, shown in Table 165, reports status information about the current
state of the debugger and the system.
Table 165. OCD Status Register (OCDSTAT)
Bit
7
6
5
4
3
2
1
0
Field
IDLE
HALT
RPEN
Reserved
Reset
0
0
0
0
R/W
R
R
R
R
Bit
[7]
IDLE
[6]
HALT
[5]
RPEN
[4:0]
Description
CPU Idle
This bit is set if the part is in Debug mode (DBGMODE is 1) or if a BRK instruction has
occurred since the last time OCDCTL was written. This can be used to determine if the CPU is
running or if it is idle.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
HALT Mode
0 = The device is not in HALT Mode.
1 = The device is in HALT Mode.
Read Protect Option Bit Enable
0 = The Read Protect option bit is disabled (Flash option bit is 1).
1 = The Read Protect option bit is enabled (Flash option bit is 0), disabling many OCD
commands.
Reserved; must be 0.
PS025015-1212
PRELIMINARY
On-Chip Debugger