Z8F1680SH020SG Datasheet, PDF (57/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
32
Table 9. Reset and Stop Mode Recovery Characteristics and Latency
Reset Type
System Reset 
(non-POR Reset)
System Reset 
(POR Reset)
System Reset with
Crystal Oscillator
Enabled
Stop Mode Recovery
Reset Characteristics and Latency
Control Registers eZ8 CPU Reset Latency (Delay)
Reset (as applicable) Reset
68 Internal Precision Oscillator Cycles after
IPO starts up
Reset (as applicable) Reset
68 Internal Precision Oscillator Cycles +
50 ms Wait time
Reset (as applicable) Reset
568–10068 Internal Precision Oscillator
Cycles after IPO starts up; see Table 141
on page 280 for a description of the
EXTLTMG user option bit.
Unaffected, except
RSTSTAT and
OSCCTL registers
Reset
4 Internal Precision Oscillator Cycles after
IPO starts up
During a System Reset or Stop Mode Recovery, the Internal Precision Oscillator (IPO)
requires 4 µs to start up. When the reset type is a System Reset, the F1680 Series MCU is
held in Reset for 68 IPO cycles. If the crystal oscillator is enabled in Flash option bits, the
Reset period is increased to 568–10068 IPO cycles. For more details, see Table 141 on
page 280 for a description of the EXTLTMG user option bit. When the reset type is a Stop
Mode Recovery, the F1680 Series MCU goes to NORMAL Mode immediately after 4
IPO cycles. The total Stop Mode Recovey delay is less than 6 µs. When a Reset occurs due
to a VBO condition, this delay is measured from the time the supply voltage first exceeds
the VBO level (discussed later in this chapter). When a Reset occurs due to a POR
condition, this delay is measured from the time that the supply voltage first exceeds the
POR level. If the external pin reset remains asserted at the end of the Reset period, the
device remains in reset until the pin is deasserted.
Note: After a Stop Mode Recovery, the external crystal oscillator is unstable. Use software to
wait until it is stable before you can use it as main clock.
At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor
disabled, except PD0 that is shared with the Reset pin. On Reset, the Port D0 pin is
configured as a bidirectional open-drain Reset. The pin is internally driven Low during
port reset, after which the user code can reconfigure this pin as a general-purpose output.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and WDT oscillator continue to function.
PS025015-1212
P R E L I M I N A R Y Reset, Stop Mode Recovery and Low-Voltage