Z8F1680SH020SG Datasheet, PDF (258/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
233
14. The software responds by writing the data to be written out to the I²C Control
Register.
15. The I²C controller shifts out the remainder of the second byte of the slave address (or
ensuring data bytes, if looping) via the SDA signal.
16. The I²C slave sends an Acknowledge by pulling the SDA signal Low during the next
High period of SCL. The I²C controller sets the ACK bit in the I²C Status Register. If
the slave does not acknowledge, see the second paragraph of Step 11.
17. The I²C controller shifts the data out by the SDA signal. After the first bit is sent, the
transmit interrupt asserts.
18. If more bytes remain to be sent, return to Step 14.
19. The software responds by asserting the stop bit of the I²C Control Register.
20. The I²C controller completes transmission of the data on the SDA signal.
21. The I²C controller sends a stop condition to the I²C bus.
Note: If the slave responds with a Not Acknowledge during the transfer, the I²C controller
asserts the NCKI bit, sets the ACKV bit, clears the ACK bit in the I²C State Register and
halts. The software terminates the transaction by setting either the stop bit (end transac-
tion) or the start bit (end this transaction, start a new one). The Transmit Data Register is
flushed automatically.
17.2.5.6. Master Read Transaction with a 7-Bit Address
Figure 45 displays the data transfer format for a Read operation to a 7-bit addressed slave.
S
Slave Address
R=1 A
Data
A
Data
A P/S
Figure 45. Data Transfer Format—Master Read Transaction with a 7-Bit Address
Observe the following steps for a Master Read operation to a 7-bit addressed slave:
1. The software initializes the MODE field in the I²C Mode Register for MASTER/
SLAVE Mode with 7- or 10-bit addressing (the I²C bus protocol allows the mixing of
slave address types). The MODE field selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IEN bit in
the I²C Control Register.
2. The software writes the I²C Data Register with a 7-bit slave address, plus the Read bit
(which is set to 1).
3. The software asserts the start bit of the I²C Control Register.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller