Z8F1680SH020SG Datasheet, PDF (155/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
130
10.7.2. Multi-Channel Timer High and Low Byte Registers
The High and Low Byte (MCTH and MCTL) registers, shown in Table 70, contain the
current 16-bit Multi-Channel Timer count value.
Zilog does not recommend writing to the Multi-Channel Timer High and Low Byte
registers while the Multi-Channel Timer is enabled. If either or both of the Multi-Channel
Timer High or Low Byte registers are written during counting, the 8-bit written value is
placed in the counter (High and/or Low byte) at the next system clock edge. The counter
continues counting from the new value.
Table 70. Multi-Channel Timer High and Low Byte Registers (MCTH, MCTL)
Bit
7
6
5
4
3
2
1
0
Field
MCTH
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FA0H
Bit
7
6
5
4
3
2
1
0
Field
MCTL
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FA1H
Bit
[7:0]
MCTH,
MCTL
Description
Multi-Channel Timer High and Low Byte
These bytes contain the current 16-bit Multi-Channel Timer count value, {MCTH[7:0],
MCTL[7:0]}.
When the Multi-Channel Timer is enabled, a read from MCTH causes the value in MCTL
to be stored in a temporary holding register. A read from MCTL returns this temporary
register when the Multi-Channel Timer is enabled. When the Multi-Channel Timer is dis-
abled, reads from MCTL read the register directory. The Multi-Channel Timer High and
Low Byte registers are not reset when TEN = 0.
10.7.3. Multi-Channel Timer Reload High and Low Byte
Registers
The Multi-Channel Timer Reload High and Low Byte (MCTRH and MCTRL) registerss,
shown in Table 71, store a 16-bit reload value, {MCTRH[7:0], MCTRL[7:0]}. When TEN
= 0, writes to this address update the register on the next clock cycle. When TEN = 1,
PS025015-1212
PRELIMINARY
Multi-Channel Timer