Z8F1680SH020SG Datasheet, PDF (161/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
136
Table 77. Multi-Channel Timer Channel Status 1 Register (MCTCHS1)
Bit
7
6
5
4
3
2
Field
Reserved
CHDEF CHCEF
Reset
0
0
0
0
0
0
R/W
R
R
R
R
R/W
R/W
Address
See note.
Note: If a 01H is in the Subaddress Register, it is accessible through Subregister 1.
1
CHBEF
0
R/W
0
CHAEF
0
R/W
Bit
[7:4]
[3:0]
CHyEF
Description
Reserved; must be 0.
Channel y Event Flag
This bit indicates if a Capture/Compare event occurred for this channel. Software can use this
bit to determine the channel(s) responsible for generating the Multi-Channel Timer channel
interrupt. This event flag is cleared by writing a 1 to the bit. These bits will be set when an
event occurs independent of the setting of the CHIEN bit. This bit is cleared when TEN=0 (TEN
is the MSB of MCTCTL1).
0 = No Capture/Compare Event occurred for this channel.
1 = A Capture/Compare Event occurred for this channel.
PS025015-1212
PRELIMINARY
Multi-Channel Timer