Z8F1680SH020SG Datasheet, PDF (328/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
303
when it reaches the maximum count of FFFFH. The OCDCNTR Register automatically
resets itself to 0000H when the OCD exits DEBUG mode if it is configured to count clock
cycles between breakpoints.
If the OCDCNTR Register is configured to generate a BRK when it counts down to zero,
it will not be reset when the CPU starts running. The counter will start counting down
toward zero after the On-Chip Debugger exits DEBUG mode. If the On-Chip Debugger
enters DEBUG mode before the OCDCNTR Register counts down to zero, the OCD-
CNTR will stop counting.
If the OCDCNTR Register is configured to generate a BRK when the program counter
matches the OCDCNTR Register, the OCDCNTR Register will not be reset when the
CPU resumes executing and it will not be decremented when the CPU is running. A BRK
will be generated when the program counter matches the value in the OCDCNTR Register
before executing the instruction at the location of the program counter.
Caution: The OCDCNTR Register is used by many of the OCD commands. It counts the number
of bytes for the register and memory read/write commands. It retains the residual value
when generating the CRC. If the OCDCNTR is used to generate a BRK, its value must
be written as a final step before leaving DEBUG mode.
Because this register is overwritten by various OCD commands, it must only be used to
generate temporary breakpoints, such as stepping over CALL instructions or running to a
specific instruction and stopping.
When the OCDCNTR Register is read, it returns the inverse of the data in this register.
The OCDCNTR Register is only decremented when counting. The mode where it counts
the number of clock cycles in between execution is achieved by counting down from its
maximum count. When the OCDCNTR Register is read, the counter appears to have
counted up because its value is inverted. The value in this register is always inverted when
it is read. If this register is used as a hardware breakpoint, the value read from this register
will be the inverse of the data actually in the register.
23.3. On-Chip Debugger Commands
The host communicates to the On-Chip Debugger by sending OCD commands using the
DBG interface. During normal operation, only a subset of the OCD commands are
available. In Debug mode, all OCD commands become available unless the user code is
protected by programming the Flash Read Protect option bit (FRP). The Flash Read
Protect option bit prevents the code in memory from being read out of the Z8 Encore! XP
F1680 Series device. When this option is enabled, several of the OCD commands are
disabled. When the Read Protect option bit is enabled, asserting the TESTMODE pad does
NOT put the Z8 Encore! XP F1680 Series MCU in Flash Test mode.
PS025015-1212
PRELIMINARY
On-Chip Debugger